1. Field of the Invention
The present invention is related to a serial/parallel data conversion apparatus and a method thereof, and more particularly to an apparatus for converting serial data into parallel data by using delay pulse and three stage registers and a method thereof.
2. Description of Related Art
Please refer to FIG. 1, which is a block diagram showing the circuit of conventional serial to parallel conversion device. In the conventional serial to parallel conversion device 1, the circuit designed for converting the serial data into the parallel data always adopts shift register 10, which includes multiple flip flops 102. The serial data SD0-SD6 are driven by serial working clock signal serial_clk of high frequency (Mbps or Gbps) and then stored into the flip flops 102 of the shift register 10 and simultaneously submitted to output terminals Q0-Q6 of the flip flops 102.
Please also refer FIG. 2. The clock signal generator 11 generates a parallel working clock signal parallel_clk according to the serial working clock signal serial_clk, wherein the serial data SD0-SD6 with the last serial data SD7 are driven by the parallel working clock signal parallel_clk and then stored in a parallel register 12, which is next to the shift register 10, and simultaneously submitted to output terminals Q0-Q7 of the parallel register 12 so as to form parallel data PD0-PD7.
However, since the conversion from serial data SD0-SD7 to parallel data PD0-PD7 is operated under high frequency, the high operation frequency might make the parallel register 12, which is next to the shift register 10, difficult to realize the logic operation, so as to cause non-logic operation between the shift register 10 and the parallel register 12, which includes multiple flip flops 122. At the same time, the parallel data PD0-PD7 outputted by the shift register 10 are only stored in the parallel register 12 and can not be delivered to the register next to the parallel register 12 since there is no additional clock signal inputted for outputting data from the parallel register 12.
Therefore, when converting from serial data SD0-SD7 to parallel data Pd0-PD7, if the additional serial working clock signal serial_clk is not inputted, the operation frequency of the register (parallel register 12) next to the shift register 10 can not be reduced, so that the frequency of the shift register 10 will become too high, and thus, the shift register 10 and the parallel register 12 will need an additional clock signal, or the parallel data PD0-PD7 will be stored in the parallel register 12 and not be delivered to the register next to the parallel register 12.